Every MAC is synthesized into one bitstream. Muxes at the PCS layer route the active MAC to each SFP+ cage, so a personality change is a CSR write — per port, at runtime. Cage 1 can run EPON while cage 2 runs GPON.
Status is stated honestly, per protocol. Nothing here is claimed until a self-checking testbench proves it.
Here's what the first board is: an FPGA with enough SerDes to run two PON ports at line rate, in a form factor that sits on a bench.
Pilots, lab units, compatibility testing, or just what you're trying to break — we answer.